The timer of STM32 is much more than just a simple "counting" tool. Center Aligned Mode is an important feature of STM32 universal and advanced timers, which provides higher accuracy and flexibility for applications such as PWM generation and motor control through a bidirectional counting mechanism.

The reason why the central alignment mode is important is that it can generate symmetrical PWM waveforms in each counting cycle, which is crucial for reducing electromagnetic noise and harmonic distortion in motor control. Of course, the most important thing is to lay the foundation for SVPWM.

1、 Working principle of central alignment mode

In the central alignment mode, the counter does not simply count unidirectionally, but first counts up to the automatic reload value (ARR), and then counts down to 0, and so on in a loop.

This bidirectional counting method generates a symmetrical counting cycle, causing the PWM signal to reach its peak at ARR/2 and form a symmetrical waveform.

Compared with the unidirectional counting mode, the biggest feature of the central alignment mode is that each complete cycle contains two counting direction transitions, which provides more opportunities for precise control of time sensitive tasks.

2、 Three central alignment modes

STM32 uses the CMS [1:0] bit field in the TIMx_CR1 register to configure three different central alignment modes, which have critical differences in update event (UEV) trigger positions and interrupt trigger counts.

The following is a comparative summary of three modes:

模式1（CMS[1:0]=01）

模式1的计数顺序是：从0开始向上计数到ARR值，然后向下计数到0，完成一个周期。

更新事件(UEV)仅在向下计数到0时触发一次，这意味着每个完整周期只产生一次更新中断。这种模式特别适合生成对称的互补PWM，如用于FOC（磁场定向控制）算法。

配置代码示例：

html复制TIM1->CR1 |= TIM_CounterMode_CenterAligned1;  // CMS[1:0]=01

Mode 2 (CMS [1:0]=10)

Mode 2 adopts the opposite counting order: count down to 0 first, and then count up to ARR value.

Unlike Mode 1, the update event in Mode 2 is triggered only once when ARR is counted up. This feature makes it suitable for application scenarios with specific timing synchronization requirements.

Mode 3 (CMS [1:0]=11)

Mode 3 is the most active central alignment mode, where the counter counts bidirectionally and update events are triggered when the counter counts down to 0 and up to ARR.

This means that each complete cycle will generate two update events, and the interrupt triggering frequency is twice that of the first two modes. This high-frequency interrupt characteristic makes it very suitable for applications that require frequent handling of timing events, which means we can change the PWM duty cycle faster.

3、 Match events with interrupt triggers

When the value of the comparison register CCR is between 0 and ARR, two matching events (CNT=CCR) will occur within one central alignment counting cycle.

The different modes determine whether these two matching events trigger the comparison event flag (such as CC4IF) and when it is triggered:

Mode 1: Set the comparison event flag only when a matching action occurs during the down counting process

Mode 2: Set the comparison event flag only when a matching action occurs during the up counting process

Mode 3: When a matching action occurs during the up and down counting process, the comparison event flag will be set

These comparison event flags can trigger interrupts or DMA requests when set, providing a flexible event response mechanism for real-time control systems.

4、 Actual application scenarios

motor control

The central alignment mode is particularly important in motor control, especially mode 1, which is widely used for PWM generation in FOC motor control. Symmetric PWM waveform can reduce electromagnetic noise and harmonic distortion of the motor, improve control accuracy and efficiency.

ADC synchronous trigger

In applications that require precise sampling timing, the different characteristics of the central alignment mode can be utilized to synchronize ADC conversion. For example, one can choose to start ADC conversion on the left or right side of the overflow point on the counter, and improve sampling accuracy by enabling conversion at the appropriate time point.

High frequency interrupt application

Mode 3 is suitable for application scenarios that require high-frequency event processing due to its characteristic of triggering two interrupts per cycle. Although this increases CPU interrupt load, it provides finer time control capabilities.

Attention: The STM32F3, STM32G4, STM32F7, STM32H7 and other series offer more advanced hardware features, such as configuring advanced timer channel output signal edge combinations to achieve ADC synchronous triggering, which can further reduce software processing and CPU involvement.

5、 Configuration examples and precautions

The basic steps to configure the STM32 timer for central alignment mode are:

Enable Timer Clock: Enable the clock of the corresponding timer through the RCC module.

Set the prescaler and automatic reload values: Set the PSC and ARR registers according to the desired frequency.

Select central alignment mode: Configure the CMS bit field of TIMx_CR1 register to select mode 1/2/3.

Set comparison value: Configure CCR register to define matching points.

Enable Interrupt/DMA: Enable interrupts or DMA requests for comparison events as needed.

Start timer: Set the CEN bit to start the counter.

Simple configuration example:

html复制// 配置TIM1为中央对齐模式1TIM1->PSC = 71;                          // 预分频器，假设系统时钟72MHzTIM1->ARR = 999;                         // 自动重装载值TIM1->CCR1 = 500;                        // 比较匹配值，50%占空比TIM1->CR1 |= TIM_CounterMode_CenterAligned1; // 设置为中央对齐模式1TIM1->CR1 |= TIM_CR1_CEN;                // 使能计数器

html复制重要注意事项：

In central alignment mode, the effective counting frequency of the timer is half of the clock frequency, as each cycle contains two counts (up and down).

When using the central alignment mode to generate PWM, the waveform symmetry is better, but the interrupt load may be higher (especially in mode 3). Different STM32 series may have slight differences in implementation details, and it is recommended to refer to the reference manual for specific models.

The three central alignment modes of the STM32 timer provide different event triggering strategies to adapt to diverse application requirements

Mode 1 focuses on triggering when counting down, suitable for FOC motor control;

Mode 2 focuses on triggering when counting upwards, used for specific synchronization scenarios;

Mode 3 provides bidirectional triggering to meet the needs of high-frequency interrupt applications.

Mastering the differences in these modes can help engineers achieve more accurate and efficient timing control solutions in scenarios such as motor control, power management, and precision measurement.